This invention relates generally to computer systems, and more particularly to computer interconnection sub-systems commonly called buses, and to techniques for establishing bus operating parameters.
As is known in the art, bus adapters and other devices are connected to a bus through bus interfaces. A bus interface is typically specifically designed for a particular type of bus, and is responsible for complying with the signaling requirements of the bus, sometimes called its xe2x80x9cbus protocolxe2x80x9d, including its electrical, physical and logical characteristics for reliable bus transfers. The bus interface generally includes bus drivers and bus receivers to send and receive, respectively, signals over the bus in accordance with the bus protocol. Essentially, each device connected to the bus has a separate instance of a bus interface for each line of the bus, each including a driver for driving that line and a receiver for sensing and resolving voltages on that line into logic states. Bus protocols are typically specified by manufacturers and often by standards-making organizations. Bus adapters include bus interfaces for each of the buses to which they are connected.
Computer system architecture has advanced dramatically in performance and complexity. In terms of performance, computer systems can achieve higher clock speeds with increased bus widths and lower bus operating voltages. Increased bus clock speeds, measured usually in megaHertz (MHz) can allow data to be transferred faster over the computer system""s buses, thereby allowing computer applications to run faster. The size of a bus, known as its width, corresponds generally to the number of data lines in the bus and determines how much data can be transmitted in parallel at the same time; thus, wider buses typically transfer data faster. Lower bus operating voltages can advantageously also reduce power consumption, which is important, for example, in miniaturization of integrated circuits and in mobile computing for extending battery operating times. Unfortunately, lower operating voltages can make bus signals more susceptible to signaling errors due to lower signal-to-noise ratios and to signal distortion. Such noise and signal distortion can make it difficult for bus receivers to differentiate correctly between data logic states, thus potentially yielding erroneous data.
Transient and other non-predictable errors in the received data signals can also arise from other causes as well, and often have a deleterious impact on computer system performance. Such errors can arise, for example, from degradation over time of bus drivers and receivers in bus interfaces. Bus errors can also arise due to non-compatibility of add-on components such as adapter cards that are integrated into the computer system after installation at a customer site, and connected to one of the computer""s buses, e.g., through xe2x80x9cplug and playxe2x80x9d operation. Where such adapter cards malfunction or simply exhibit operating parameters unanticipated by the original computer manufacturer, data transfer errors can arise on the bus to which they are connected. Such bus errors can result in lost or corrupted data or hanging of the bus protocol so as to prevent completion of a bus transaction. In extreme cases, bus errors can cause system crashes.
Accordingly, while current computer systems perform reasonably well, it would be desirable to improve bus operating and signaling parameters so as to avoid or at least lessen difficulties with respect to bus transfer errors and otherwise to improve bus performance. Such bus operating and signaling parameters are determined, at least in part, by signal characteristics in bus drivers and bus receivers.
Examples of signal characteristics include rise time and fall time of the driver output. xe2x80x9cRise timexe2x80x9d refers to the time period between the point at which a driver output starts transitioning from a low voltage state to a high voltage state and the point at which this signal reaches the high voltage state. On the other hand, xe2x80x9cfall timexe2x80x9d refers to the time period between the point at which a signal starts transitioning from a high voltage state to a low voltage state and the point at which this signal reaches the low voltage state. The rise time characteristic is important to computer system operation because rise time is related to the maximum bus speed, one of the more important bus operating parameters.
Rise time is dictated typically by the high frequency characteristics of the output transistor of the driver. When developing operating specifications for a bus, a computer system designer may determine the shortest typical rise time that the output transistor of the driver will achieve, and then specify the maximum bus speed for all buses using that type of driver based on that lowest rise time. Accordingly, rise time or fall time performance by a driver often is not controlled specifically; rather, the natural rise time and fall time characteristics of the output transistor circuit in the driver are accepted and are used to dictate overall system bus performance. Some designs, however, attempt to control rise time. One approach used in the prior art to control rise time characteristics of the output transistor of the driver is to design into the driver a relatively small resistance in series with an input circuit of the output transistor. The input circuit with the added resistance exhibits a higher resistance-capacitance time constant than a similar circuit without that resistance, which has the effect of slowing down the rise time. One problem with this approach, however, is that such resistances are generally provided as internally integrated devices within the circuit. The tolerance on such a resistance, as currently achievable by standard semiconductor processing techniques, is relatively poor, typically on the order of about 15 percent. This relatively poor tolerance provides too much variation in the rise time characteristics of the transistor to be effective in controlling that parameter.
U.S. Pat. No. 5,657,456 issued to Gist and Coyle on Aug. 12, 1997, entitled xe2x80x9cSemiconductor Process Power Supply Voltage and Temperature Compensated System Bus Driver Rise and Fall Time,xe2x80x9d and incorporated herein by reference, discloses a driver circuit having an input terminal fed by a logic signal and an output terminal including means for setting a rise time for a signal driven from the driver. An external resistor determines the rise time. It would be possible to adjust rise and fall times in that patent by manually swapping out the external resistor for one of a different resistance value, that is, manually disconnecting the external resistor and manually connecting a replacement having a different resistance value.
While potentially effective in controlling rise times, the technique disclosed in that patent has a number of drawbacks. For example, it requires a trained technician to perform modifications to the printed circuit board on which the external resistor is mounted. This procedure may require removal of the computer system from a customer""s facility so that the work can be performed at a repair location. There is an attendant risk that the procedure may damage the board or other mounted components. Moreover, such repair may be time consuming and expensive, and typically would require an inventory of replacement resistors. Customers often rely on their computer systems to such an extent that computer xe2x80x9cdown timexe2x80x9d associated with such repair is often unacceptable.
Another example of an important signal characteristic is the threshold voltage at the receiver, which refers to the voltage level between the line high voltage and the line low voltage, above which the receiver resolves the signal into one logic state, and below which into the other logic state. The threshold voltage is often slightly different for each logic state, with the difference between the two threshold voltage levels being an area of uncertainty or indeterminacy. The values of these two threshold voltage levels, and the area of uncertainty between them, can significantly impact the effectiveness with which the receiver resolves received bus signals into logic states. U.S. Pat. No. 5,406,147 issued to Coyle and Gist, entitled xe2x80x9cPropagation Speedup By Use of Complementary Resolver Outputs in a System Bus Receiverxe2x80x9d, and incorporated herein by reference, discloses a mechanism for controlling threshold voltage of a system bus receiver. In that patent, a resolver circuit is fed a bus signal and a reference voltage. A circuit including a sense-amplifier is used to provide an output based on the relationship of the magnitude of the bus signal to that of the reference voltage. Thus, the threshold voltage value is set at a fixed value determined by the value of reference voltage. While the technique disclosed in that patent may be effective in setting the threshold voltage, it would be desirable to control more readily the reference value so to vary the threshold value for particular applications and improve bus operation.
Other patents related to those referenced herein include U.S. Pat. Nos. 5,479,123; 5,534,811; 5,687,330; 5,634,014; 5,654,653; 5,359,235; and 5,461,330 also deal with various aspects of setting bus operating and signaling parameters. The disclosures of those patents are incorporated herein by reference.
Accordingly, it would be desirable to provide a technique for adjusting bus operating and signaling parameters in a straightforward manner, which permits bus transfer errors to be corrected and/or bus performance improved, while also overcoming the drawbacks of prior art techniques.
The invention resides in a system for programmatically adjusting electrical characteristics of a bus interface so as to modify bus operating and signaling parameters. The adjustment is effected by a control module or mechanism, responsive to a digital signal, for setting the characteristic""s value. For example, the electrical characteristic can be a voltage that is determinative, e.g., of any of the following bus operating and signaling parameters: driver output rise time, driver output fall time, driver voltage limits, driver propagation time, receiver threshold voltage levels, or termination resistance. The digital signal can be generated, for example, by a computer-executable program, a controller, or other such device, that applies the digital signal to the control mechanism, for example, via a JTAG interface/controller.
Accordingly, a computer system can be repaired, and/or its performance improved, by having one or more bus operating and signaling parameters adjusted. The adjustment can serve, for example, to correct bus transfer or signaling errors, to insure bus transfers fall within a predetermined target operating envelop, and/or to optimize bus performance. The adjustment can be achieved automatically and dynamically, in real time, e.g., through software control, often without significant involvement by a service technician, offsite repair facilities, or significant downtime of the computer system.
Another aspect of the invention provides a bus interface having a bus driver for driving a corresponding bus line with a driver output signal responsive to an input signal. The driver output signal has a signal parameter responsive to a control signal. A control module generates the control signal for controlling the signal parameter. The control module includes a signal generator for generating the control signal, and a resistance circuit characterized by a resistance value, which is programmably set in response to a digital signal, and with respect to which the control signal varies. A digital signal generator can be employed to generate the digital signal. The digital signal generator can include, e.g., a processor executing a program for setting the digital signal so as to cause adjustment of the control voltage and thereby controlling the signal parameter.
Yet another aspect of the invention provides a bus interface having a bus receiver for receiving a bus signal over a corresponding bus line. The bus receiver is characterized by an operating parameter, such as a threshold voltage, for use in resolving the bus signal into digital logic states. The threshold voltage is responsive to a control signal. A control module generates the control signal for controlling the threshold voltage of the receiver. The control module includes a signal generator for generating the control signal, and a resistance circuit characterized by a resistance value, which is programmably set in response to a digital signal, and with respect to which the control signal varies. The digital signal generator can include, e.g., a processor executing a program for setting the digital signal so as to cause adjustment of the control voltage and thereby controlling the signal parameter.
In another aspect of the invention, the bus interface having the driver and/or receiver, as just described, can be provided with resistance circuitry, including a plurality of resistance cells switchable between active and inactive states in response to the digital signal for setting the control signal. In an exemplary embodiment, the resistance circuitry can include first and second voltage dividers connected in parallel. The first voltage divider can include a serial arrangement of a first resistor and a second resistor having an adjustable resistance. The second voltage divider can include a serial arrangement of a third resistor having a programmable resistance, and a fourth resistor having an adjustable resistance. The resistance of the second and fourth resistors being set, e.g., equal to one another, in response to a second control voltage. The control voltage for controlling the driver output signal is tapped from a node located between the third and fourth resistors. The third resistor can include a programmable, variable resistance circuit having a plurality of resistance cells each characterized by a resistance value. Each resistance cell can include a variable resistance and a switch, e.g., a transistor switch, responsive to a switching signal, for individually connecting the variable resistance into the resistance circuit and thereby individually rendering the resistance cells active. The bus interface can further have a controller, responsive to the digital signal, for generating the switching signals. With this arrangement, the control voltage varies in relation to the number of active resistance cells.
Accordingly, a technique is provided for adjusting bus operating and signaling parameters in a straightforward manner, which permits bus transfer errors to be corrected and/or bus performance improved, while also overcoming drawbacks of prior art techniques.